In general, a semiconductor memory device includes a redundancy circuit for repairing a defect on a semiconductor substrate or replacing a defective cell generated while the semiconductor memory device is fabricated with a redundancy cell. That is, the semiconductor memory device includes a redundancy memory cell array in addition to a memory cell array.
The semiconductor memory device including the redundancy memory cell array can include a plurality of fuse circuits in order to memorize each bits of the addresses indicating the memory cell array. When the memory cell array has a defective cell, the fuse circuits can be programmed such that fuses of the fuse circuits are cut in response to the address of the defective memory cell in a test process.
When a voltage for driving the semiconductor memory device is applied to the semiconductor memory device, the fuse circuits output fuse status information representing whether the fuses are cut. The fuses used in the semiconductor memory device can be made of a metal such as aluminum and copper, in general. The fuses can be cut by irradiating a laser thereon. Even when the fuses are cut, however, fuse remnants can remain, which may function as a resistor having a very large resistance value. The semiconductor memory device replaces defective memory cells with redundancy memory cells in response to the fuse status information.
FIG. 1 is a circuit diagram of a conventional fuse circuit 100, Referring to FIG. 1, the fuse circuit 100 includes a fuse 110, a status information output unit 130, and a holding and outputting unit 150. The conventional fuse circuit 100 is explained below on the assumption that the fuse 110 has been cut.
When a voltage for driving a semiconductor memory device is applied to the fuse circuit, a constant voltage signal PVCCH is set to a low level. The constant voltage signal PVCCH is generated by a constant voltage generator (not shown). The constant voltage signal generator includes a load having a large value. Accordingly, the constant voltage signal generator generates the constant voltage signal PVCCH which is gradually increased from a low level to a high level as the driving voltage is increased to a predetermined voltage level.
The constant voltage signal PVCCH set to a low level is inverted by a first inverter INV1 and inputted to the gate of a PMOS transistor P1 and the gate of a first NMOS transistor N1 such that the PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on. Accordingly, the status information output unit 130 outputs a low level signal to a node A.
The holding and outputting unit 150 outputs a fuse status information signal R_EN having a high level to a node B. The high level fuse status information signal R_EN is inputted to a second NMOS transistor N2 to turn on the second NMOS transistor N2.
As the driving voltage is applied and increased to the predetermined voltage level, the constant voltage signal PVCCH is gradually increased to a high level. The constant voltage signal increased to a high level is inverted by the first inverter INV1 and inputted to the gates of the PMOS transistor P1 and the first NMOS transistor N1 to turn on the PMOS transistor P1 and to turn off the first NMOS transistor N1.
The source of the PMOS transistor P1 is being floated because the fuse 110 has been cut. Accordingly, the node A and a node B are maintained at a low level and a high level, respectively, and the second NMOS transistor N2 is still turned on. Here, a current path having a large resistance value due to remnants of the cut fuse, that is, a current path consisting of a power supply voltage VDD, the fuse remnants, the PMOS transistor P1, the second NMOS transistor N2 and a ground voltage, is generated in the fuse circuit because both the PMOS transistor P1 and the second NMOS transistor N2 are turned on. This current path generates unnecessary leakage current to deteriorate power performance of the semiconductor memory device.